1. Field of the Invention
This invention relates to eliminating the latch-up effect in integrated circuits and particularly to the use of Schottky barrier diodes to prevent latch-up in parasitic PNPN structures causing such as in CMOS integrated circuits.
2. Description of the Prior Art
In complementary metal oxide silicon (CMOS) integrated circuits fabricated in bulk silicon, a PNPN structure exists. When an external noise pulse, signal overshoot transient or transient radiation pulse occurs, current may forward bias one of the PN junctions. The PNPN structure or four-layer structure may be switched into a low impedance state called latch-up. The four-layer structure may be viewed as a PNP bipolar transistor coupled to an NPN transistor where the base of the PNP transistor is coupled to and forms a collector of the NPN transistor, and the emitter of the PNP transistor is coupled to and forms a base of the NPN transistor. Conditions for latch-up exist in the four-layer structure when the current gain .beta. of the PNP transistor multiplied by the .beta. of the NPN transistor is greater than one.
Latch-up is a serious problem in CMOS integrated circuits because N and P channel transistors are located close to one another. in very high speed integrated (VHSI) devices, the spacing between N and P channel transistors is very small. Typically, a substrate of N material or a layer of N-type material has P-type MOS field effect transistors formed therein. A P-type region or P tub is formed in the N-type substrate or N-type layer. N-type transistors are formed in the P region or P tub. A four-layer structure is formed including the drain or source of the P-type transistor, the N-type substrate, the P tub and the drain or source of the N-type transistor. Additional PN junctions are formed when the gate input is protected from overvoltage by a protective diode formed in the P tub or in the substrate.
In U.S. Pat. No. 4,300,152, which issued on Nov. 10, 1981 to Martin P. Lepselter, a complementary field effect transistor integrated circuit was shown in FIG. 4 where in place of a P-channel MOS transistor, a Schottky barrier insulated gate field effect transistor was used. The Schottky barrier insulated gate field effect transistor provided a source and drain which when forward biased with respect to the N substrate was incapable of injecting minority carriers (electron vacancies or holes) into the N-type substrate. Without minority carrier injection no transistor action occurs. In effect, the four-layer structure is reduced to a three-layer structure NPN with the last N being the substrate material. The drain and source of the Schottky barrier insulated gate field effect transistor (IGFET) does not act as a P-type region even though the resulting field effect transistor is P-type.
One example of an insulated gate field effect transistor using Schottky barrier contacts is described in a publication entitled "SB-IGFET: An Insulated-Gate Field Effect Transistor Using Schottky Barrier Contacts For Source And Drain", Proceedings of IEEE, Vol. 56, August 1968, pp. 1400-1402, by M. P. Lepselter and S. M. Sze.
When using a Schottky barrier IGFET in a CMOS circuit such as, for example, for the P-channel transistor, the source is reverse-biased which interferes with the drain source conduction when the transistor is turned on or attempted to be turned on. The Schottky barrier height is an impediment to current flow across the channel region, and even when current flows it is limited due to the barrier height. In addition, due to the high fields generated by the barrier height, the Schottky barrier junction near the surface at both the drain and source may experience high leakage currents, such as for example with a platinum silicide-silicon junction.
It is therefore desirable to provide a field effect transistor which does not inject minority carriers into the substrate when forward biased at its drain or source and at the same time does not limit the current passing between the drain and source due to the barrier height of a Schottky barrier.
It is further desirable to reduce leakage currents due to a Schottky barrier diode incorporated in a field effect transistor as its source or drain.
It is further desirable to provide a CMOS circuit which may be fabricated in bulk silicon that incorporates Schottky barrier diodes in parallel to the source or drain to reduce latch-up while having field effect transistors with high drain to source conduction at low currents.
It is further desirable to provide input and output networks using Schottky diodes to minimize minority current injection at time the diodes are forward biased.